Silicon Logic Formal Verification - Full Time

This full-time position in Santa Clara, CA focuses on Silicon Logic Formal Verification within CPU, Fabric, and Accelerator design. Responsibilities include formal verification of the architecture and microarchitecture of high-performance designs, collaborating with architects and RTL design engineers, proving functional and security properties, developing formal abstract models, and creating innovative verification flows. The ideal candidate should have a solid understanding of temporal assertion properties, experience with model checking tools, and familiarity with interactive theorem provers. Strong problem-solving, communication, and organizational skills are required, along with a degree in a technical subject area at the PhD, Master's, or Bachelor's level.